1. Field of the Invention
The present invention relates to a vertical MOS transistor having a trench structure.
2. Description of the Related Art
FIG. 2 shows a schematic cross sectional view of a vertical MOS transistor having a conventional trench structure. A semiconductor substrate is prepared in which a low concentration first conductivity type layer 2 is epitaxially grown on a first conductivity type high concentration substrate 1, which becomes a drain region. A second conductivity type diffusion region 3 that is referred to as a body region is formed from a surface of the semiconductor substrate by impurity injection and high temperature heat treatment at a temperature equal to or greater than 1,000° C. In addition, a first conductivity type, high concentration impurity region 7 that becomes a source region, and a second conductivity type, high concentration body contact region 8 for fixing the electric potential of the body region by ohmic contact are formed from the surface. The first conductivity type source region and the second conductivity type body contact region are normally taken as having the save electric potential here. Accordingly, a layout with surface contact like that of FIG. 2 may be used. The first conductive type high concentration impurity region 7 and the second conductivity type high concentration body contact region 8 are electrically connected by one contact hole formed on the source region and on the body contact region. Single crystal silicon is then etched, completely passing through the first conductive source region and forming a silicon trench 9. A gate insulator film 5 and polycrystalline silicon 6 that becomes a gate electrode and that contains a high concentration impurity are embedded within the silicon trench. Further, a first conductivity type, high concentration region of a rear surface of the semiconductor substrate is connected to a drain metallic electrode (not shown in FIG. 2).
A structure like that described above can be made to function as a vertical MOS transistor that controls current flowing from the drain region comprising the first conductivity type high concentration region of the rear surface side and the first conductivity type epitaxial region, to the source region comprising the first conductivity type high concentration region of the front surface side by the gate that is embedded within the trench, through the gate insulator film of a trench sidewall. This method can apply to both N-channel and P-channel types by reversing the conductivity types between N and P.
Further, vertical MOS transistors having this trench structure have characteristics whereby it is possible to apply planar direction microprocessing techniques because a channel is formed completely in the vertical direction. Accordingly, the surface area occupied by planar transistors has become smaller together with advances in microprocessing techniques, and there is a recent trend in which the amount of drain current flowing per unit surface area of an element has been increasing.
In practice, a MOS transistor having an increased channel width, an increased amount of drain current, and an arbitrary driving performance is made by turning back a cross sectional structure like that of FIG. 2 a plurality of times (refer to U.S. Pat. No. 4,767,722).
However, with this type of vertical MOS transistor structure, there is a high electric field at an edge of the drain side, in the vicinity of a gate oxide film of the body region that becomes the channel, when the drain voltage becomes equal to or greater than the withstand voltage of the vertical MOS transistor, avalanche damage develops, and current flows. For cases where this type of damage repeatedly develops due to static electricity, noise, or the like, defects or levels may develop in this portion, and degradation of the transistor characteristics may develop. A problem thus exists in the long term reliability of the transistor characteristics with this type of conventional structure.